In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been, and continues to be, efforts toward scaling down the device dimensions on semiconductor wafers. In order to accomplish such a high device packing density, smaller features sizes are required. This may include the width and spacing of interconnecting lines and the surface geometry such as the corners and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which, for example, a silicon wafer is coated uniformly with a radiation-sensitive film (e.g., a photoresist), and an exposing source (such as ultraviolet light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template (e.g., a mask or reticle) to generate a particular pattern. The exposed pattern on the photoresist is then developed with a solvent called a developer which makes the exposed pattern either soluble or insoluble depending on the type of photoresist (e.g., positive or negative resist). The soluble portions of the resist are then removed, thus leaving a photoresist mask corresponding to the desired pattern on the wafer for further processing.
Exposure of photoresists is performed typically with optical lithography. The minimum resolution achievable with a projection lithography tool is a function of the exposure wavelength and the resolving power or numerical aperture of the lens system. As lithography tool manufacturers have reduced the energy of the imaging radiation (for example, from 436 nm wavelengths to 248 nm wavelengths), the photoresist chemistry has changed as well. For example, traditional photoresist materials were supplanted by chemically amplified resist materials. As device feature sizes continue to decrease (e.g., down to less than 100 nm), lithography systems employing even shorter exposure wavelengths will be utilized (for example, 193 nm ArF or 157 nm F2 excimer laser sources).
As highlighted above, the resolution of the lithography system may be improved by decreasing the imaging wavelength and/or increasing the numerical aperture of the lens system. Such solutions, however, tend to limit the ability to keep the photomask image in focus throughout the entire thickness of the resist film (e.g., a reduction in the depth of focus). Simply reducing the resist thickness is not always possible, since if the resist is too thin it can not function effectively as a mask for subsequent pattern transfer to the underlying material.
One solution to the above problem is to employ a bi-layer photoresist composed of an underlying layer and an overlying imaging layer, as illustrated in prior art FIG. 1. In the exemplary bi-layer resist 10 (sometimes called a multi-layer resist), an imaging layer 12 comprises a thin layer which is sufficiently thin to have the entire image focused therethrough during an exposure 14 thereof. Upon development of the imaging layer 12, resulting in the structure of prior art FIG. 2, the now exposed portion 16 of the underlying layer 18 is subjected to an etch process 20 (e.g., either wet or dry) to “develop” the underlying layer 18. The etch process employed with respect thereto is substantially selective with respect to both the remaining imaging layer 12 and an underlying material 22 to be processed (hereinafter referred to as the “process layer”), thereby resulting in a patterned resist 24, as illustrated in prior art FIG. 3.
During one or more portions of the above resist patterning process, a resist pattern inspection is performed in which the development of the bi-layers 12, 18 are evaluated to determine whether the development is sufficiently defect free to proceed with further processing. For example, after the development of the imaging layer 12 and prior to etching of the underlying layer 18, if a defect is identified, the imaging layer 12 may simply be removed and re-applied with the pattern transfer process being repeated. If, however, a defect is found after “development” of the underlying layer 18, re-work of the bi-layer is not desirable since such rework may undesirably result in the formation of shadow patterns in the underlying process layer 22.
For example, as illustrated in prior art FIG. 4A, the patterned bi-layer resist 24 is shown overlying the process layer 22. In many cases, if the etch of the imaging layer 12 is not substantially selective with respect to the exposed process layer 22, the removal of the imaging layer 12 during rework 26 causes an etching or gouging of the process layer 22 in an exposed portion 28, as illustrated in prior art FIG. 4B. Once the new bi-layer resist is deposited, exposed and patterned, the etching or gouging will have an impact upon its subsequent processing, thereby leading to shadow patterns as alluded to above. The above problem is pronounced in damascene type processing when the underlying layer 22 to be processed is a cap or etch stop type layer which contains silicon therein, and the imaging layer 12 also employs silicon for selectivity with respect to the underlying layer 18 of the bi-layer resist 24. In such circumstances, the chemistry employed to remove the imaging layer 12 during re-work is not selective with respect to the process layer 22 and the etching or gouging thereof is significant.
Therefore there is a need in the art for a method of reworking bi-layer resists without such rework impacting the underlying process layer.